It is the task of the user logic to sample the module's data output into a register when valid_o is asserted as it The valid_o signal is set for one clock cycle indicating that data_o contains a valid random byte. This clock is also used to sample the entropy sources. The neoTRNG uses a single clock domain driven by clk_i. Of course this highly depends on the actual configuration of the TRNG. ⚠️ Keeping the neoTRNG permanently enabled will increase dynamic power consumption and might alsoĬause local heating of the FPGA chip. ⚠️ Note that the neoTRNG cannot be rtl-simulated due to it's combinatorial loops. Valid_o : out std_ulogic - data_o is valid when set NUM_INV_DELAY : natural - additional inverters to form cell's long path, has to be evenĬlk_i : in std_ulogic - global clock lineĮnable_i : in std_ulogic - unit enable (high-active), reset unit when lowĭata_o : out std_ulogic_vector( 7 downto 0) - random data byte output NUM_INV_INC : natural - number of additional inverters in next cell (short path), has to be even NUM_INV_START : natural - number of inverters in first cell (short path), has to be odd NUM_CELLS : natural - total number of ring-oscillator cells The top entity is neoTRNG, which can be instantiated directly without the need for any special libraries. The whole design is based on a single VHDL file ( rtl/neoTRNG.vhd). technology, vendor and platform agnostic.tiny hardware footprint (less than 70 LUTs).? Feedback from the community is highly appreciated! Where the neoTRNG is implemented as a default processor SoC module. ℹ️ This project is a "spin-off" project of the NEORV32 RISC-V Processor, Implemented in the user logic or the application software. Sophisticated post-processing like advanced whitening, health-monitoring or even tampering-detection should be Note that the neoTRNG only provides a "random PHY" - an interface to the raw physical entropy source. Synthesize the TRNG for any FPGA platform. The architecture provides a technology-agnostic implementation that allows to
TINY CC MAKER GENERATOR
The neoTRNG provides a small and high-quality true random number generator (TRNG) that is based on free-runningĪnd cross-coupled ring-oscillators.
A Tiny and Platform-Independent True Random Number Generator for any FPGA.